A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

By Kevin Zhang, U. Bhattacharya, Zhanping Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Yih Wang, B. Zheng, Mark T. Bohr. IEEE Journal of Solid-State Circuits, 2005

325 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/1fb7f65a0babb269747feca01f5e7a60209e8252

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In Electrical and Electronic Engineering

1. Wilfried E. Haensch
2. Chris Hyung-Il Kim

Citations in the corpus

• An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches (2008, background): “Instead of being tied to a fixed higher supply, SRAM arrays could also use dynamically modulated supplies [3], [4] that are pulsed to different levels when a read or write event occurs.”
• A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory (2013, methodology): “is dynamically controlled on a column-by-column basis [29].”