A delay model and speculative architecture for pipelined routers

By Li-Shiuan Peh, William (Bill) J. Dally. Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, 2001

578 citations recorded by the source corpus.

This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary routers, the specific flow control method employed the delay of the flow control credit path, and the sharing of crossbar ports across virtual channels. Motivated by this model, we introduce a microarchitecture for a speculative virtual-channel router that significantly reduces its router latency to that of a brown hole router. Simulations using our pipelined model give results that differ considerably from the commonly assumed 'unit-latency' model which is unreasonably optimistic. Using realistic pipeline models, we compare wormhole and virtual-channel flow control. Our results show that a speculative virtual-channel router has the same per-hop router latency as a wormhole router while improving throughput by up to 40%.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/febe6e5ca8281767968037244347ee17cd2e93a3

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Citations in the corpus

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, background): “by speculatively allocating resources to move the latency associated with resource allocation and multiplexing off the critical path at low traffic loads [110], [133], or through advanced reser-”
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling (2012, methodology): “Our method optimizes for minimum energy given a delay requirement, as opposed to logical-effort based approaches employed by existing models [18] [32] [33], which optimize for minimum delay, oblivious to energy.”
A case for bufferless routing in on-chip networks (2009, methodology): “The baseline router we assume in this w ork is similar to that used in [30] employs several features to redu c router latency for each flit, including speculation [44, 39].”
Orion: a power-performance simulator for interconnection networks (2002, methodology): “Routers are pipelined in accordance to the router delay model proposed in [15].”
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, background): “As discussed earlier, various routers have been proposed with differing levels of speculation and pipeline stages [13, 26, 28].”
CACTI 6.0: A Tool to Model Large Caches (2009, methodology): “However, based on the process technology and the router model, the too l will calculate the maximum possible network frequency [11].”
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006, methodology): “Lower-latency router architectures have been proposed which parallelize the RT, VA and SA using a method known as speculative allocation [28].”
GARNET: A detailed on-chip network model inside a full-system simulator (2009, background): “The VC and switch allocators currently implemented are separable [25] with the local and global arbitration being round-robin in nature.”
A detailed and flexible cycle-accurate Network-on-Chip simulator (2013, methodology): “The delay of the VC allocation pipeline stage can effectively be hidden by employing speculative switch allocation [18] .”