CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing

By G. Ramanathan, Zhixian Chen, Navab Singh, Kaustav Banerjee, Sungjoo Lee. IEEE Electron Device Letters, 2011

185 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/8ca1371b0b87000baad33fde79537a29d4b06a77

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In Biomedical Engineering

1. Alan C. Seabaugh

In Electrical and Electronic Engineering

1. Luca Selmi
2. David Esseni
3. Hao Lu
4. Alan C. Seabaugh

Citations in the corpus

• InAs–Si Nanowire Heterojunction Tunnel FETs (2012, background): “For all field-effect devices, electrostatics play an important role, and wrap-gate geometry can substantially improve TFET performance [10].”
• Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors (2013, background): “5 V) for the n-TFET are obtained, distinctly higher than for most reported Si TFETs [7], [9], [10], [15], [16].”
• Tunnel Field-Effect Transistors: State-of-the-Art (2014, background): “are given for Si in [26], [29], [31] and for InGaAs in [47].”