3D silicon integration

By J. Knickerbocker, P. Andry, B. Dang, R. Horton, Chirag S. Patel, R. Polastre, Katsuyuki Sakuma, E. Sprogis, C. Tsang, B. Webb and 1 more. Electronic Components and Technology Conference, 2008

250 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/658dd8ca33cea6e97dcd96d377c458c47411e7ac

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In Electrical and Electronic Engineering

1. John H. Lau
2. Erik Jan Marinissen
3. Yervant Zorian

Citations in the corpus

• Thermal management of 3D IC integration with TSV (through silicon via) (2009, background): “There are many critical issues of 3D IC integration [1-14], e.”
• Testing 3D chips containing through-silicon vias (2009, background): “There are many different variants of TSV types, process steps, and stacking options [3, 18, 19].”
• TSV manufacturing yield and hidden costs for 3D IC integration (2010, background): “In the development of 3D IC integration, at least the following must be noted and understood: [1-41]”