8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

By Uksong Kang, Hoeju Chung, Seongmoo Heo, D. Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, J. Ahn, D. Kwon and 11 more. IEEE Journal of Solid-State Circuits, 2009

475 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/b0429923913748ec4b90689a2658c7d294a6776f

How researchers see this paper

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In Electrical and Electronic Engineering

1. Luca Benini
2. Erik Jan Marinissen
3. Yervant Zorian
4. Wim Dehaene
5. Giovanni De Micheli
6. Srinivasan Murali

Citations in the corpus

• Testing 3D chips containing through-silicon vias (2009, background): “Among the early applications are CMOS image sensors stacked on their corresponding read-out and digital processing circuitry, and stacks of memories [12].”
• Design Issues and Considerations for Low-Cost 3-D TSV IC Technology (2010, methodology): “Variants of 3-D technologies have recently been introduced in application areas such as DRAM stacking [2], imagers [3], [4], SSDs (Solid-StateDrives) [5].”