Larrabee: a many-core x86 architecture for visual computing

By L. Seiler, Douglas M. Carmean, Eric Sprangle, Tom Forsyth, M. Abrash, Pradeep K. Dubey, Stephen Junkins, Adam T. Lake, Jeremy Sugerman, Robert Cavin and 4 more. ACM Transactions on Graphics, 2008

878 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Computer Vision and Pattern Recognition, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/9efc63eb4171f71f02eff3470ac1cf1b49d36245

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

In Computer Vision and Pattern Recognition

In Hardware and Architecture

Citations in the corpus

Sort vs. Hash Revisited: Fast Join Implementation on Modern Multi-Core CPUs (2009, background): “In the near term, future processors will adopt wider SIMD execution (such as 256-bit for AVX [21] and 512-bit for Larrabee [34]).”
State-of-the-art in heterogeneous computing (2010, methodology): “The upcoming Larrabee [31] GPU from Intel can be considered a hybrid between a multi-core CPU and a GPU.”
Thread motion: fine-grained power management for multi-core systems (2009, background): “However, traditional DVFS scaling, which is initiated by the operating system (OS), has two primary drawbacks: First, OS scheduler sampling intervals are on the millisecond time scale, while computational requirements can vary on the nanosecond time scale due to events such as cache misses.”
Exascale Computing Technology Challenges (2010, background): “This was true for NVidia GPU solutions and possibly for heterogeneous manycore architectures like Intel’s Larrabee/Knight’s Corner[10].”
3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs (2010, methodology): “Although we focus on CPU and GPU, the formulation developed and described in this section is applicable to a broad range of computing devices such as Intel Larrabee [8], etc. DZ Y DX (say of dimension dim 3, dim3D , dim3perform the computation, each block is loaded into the onchip memory, and ke”
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU (2010, methodology): “Larrabee: a many-core x86 architecture for visual computing.”
The multikernel: a new OS architecture for scalable multicore systems (2009, background): “Future hardware will comprise fewer chips but exhibit network effects inside the chip, such as with ring [38, 61] and mesh networks [68, 70].”
FAST: fast architecture sensitive tree search on modern CPUs and GPUs (2010, methodology): “mance. We also evaluate FAST search algorithm on the Intel Many-Core Architecture Platform (MICA), a Larrabee [ 29 ] based silicon platform for many-core research and software development.”
Efficient implementation of sorting on multi-core SIMD CPU architecture (2008, methodology): “Second in the future, we will have 256-bit wide SIMD instructions [12] and even wider [20].”
Graphics processing unit (GPU) programming strategies and trends in GPU computing (2013, background): “Intel have also developed other highly parallel architectures, including the Larrabee [21] based on simple and power-efficient x86 cores, the Single-chip Cloud Computer (SCC) [10], and the 80-core tera-scale research chip Polaris [24].”
Accelerating critical section execution with asymmetric multi-core architectures (2009, background): “Since chips with 8 and 16 small cores are already in the market [22], and chips with 32 small cores are being built [47, 38], we believe ACS can be a feasible and effective option to improve the performance of workloads that use fine-grained locking in nearfuture multi-core processors.”
PacketShader: a GPU-accelerated software router (2010, methodology): “For example, Intel has recently introduced Larrabee, the many-core x86 GPU architecture with full cache coherency [45].”
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness (2009, background): “Intel’s next generation of graphics processors will support more than 900 Gflop/s [26].”
PyCUDA and PyOpenCL: A scripting-based approach to GPU run-time code generation (2009, background): “Graphics Processing Units (GPUs) [6, 28, 44] promise tremendous advantages in throughput over conventional processor architectures, ideally resulting in a large reduction of execution time for suitable compute-or bandwidth-bound algorithms.”