John Kim
Computer Networks and Communications · International Symposium on Computer Architecture · 2007–2013
A researcher in the Science corpus: 5 papers; trusts 2 researchers and is trusted by 4 researchers here, as inferred from the citation graph.
Subfields
- Computer Networks and Communications — 17 citations into it; #3,861 of 9,886 by trust here, #4,757 by citations
Whom John Kim trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
- William (Bill) J. Dally
- Chrysostomos Nicopoulos
- Brian Towles
- Tobias Bjerregaard
- Li-Shiuan Peh
- Sangyeun Cho
Who trusts John Kim overall
- Maciej Besta
- Torsten Hoefler
- William (Bill) J. Dally
- James D. Balfour
- Changho Hwang
- Thomas Moscibroda
Papers from John Kim's perspective
Ordered by how strongly the researchers John Kim trusts endorse each paper. Same corpus, a different order for every researcher.
- Route packets, not wires: on-chip interconnection networks (Proceedings - Design Automation Conference)
- Analysis of power consumption on switch fabrics in network routers (Proceedings - Design Automation Conference)
- Dynamic voltage scaling with links for power optimization of interconnection networks (The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.)
- Niagara: a 32-way multithreaded Sparc processor (IEEE Micro)
- Flattened Butterfly Topology for On-Chip Networks (Micro)
- ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (Micro)
- On-Chip Interconnection Architecture of the Tile Processor (IEEE Micro)
- An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS (2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers)
- GARNET: A detailed on-chip network model inside a full-system simulator (IEEE International Symposium on Performance Analysis of Systems and Software)
- Analyzing CUDA workloads using a detailed GPU simulator (IEEE International Symposium on Performance Analysis of Systems and Software)
Their papers
- Flattened butterfly: a cost-efficient topology for high-radix networks (2007) — 489 citations
- Technology-Driven, Highly-Scalable Dragonfly Topology (2008) — 850 citations
- Firefly: illuminating future network-on-chip with nanophotonics (2009) — 429 citations
- A detailed and flexible cycle-accurate Network-on-Chip simulator (2013) — 802 citations
- Flattened Butterfly Topology for On-Chip Networks (2007) — 475 citations