Lei Jin
Hardware and Architecture · with Cho · 2006
A researcher in the Science corpus: 1 paper; trusts 6 researchers and is trusted by 3 researchers here, as inferred from the citation graph.
Subfields
- Hardware and Architecture — 10 citations into it; #930 of 1,551 by trust here, #1,153 by citations
- Computer Networks and Communications — 9 citations into it; #6,577 of 9,886 by trust here, #7,140 by citations
Whom Lei Jin trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Who trusts Lei Jin overall
Papers from Lei Jin's perspective
Ordered by how strongly the researchers Lei Jin trusts endorse each paper. Same corpus, a different order for every researcher.
- Managing Wire Delay in Large Chip-Multiprocessor Caches (Micro)
- An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (ASPLOS X)
- Niagara: a 32-way multithreaded Sparc processor (IEEE Micro)
- Predicting inter-thread cache contention on a chip multi-processor architecture (International Symposium on High-Performance Computer Architecture)
- Optimizing replication, communication, and capacity allocation in CMPs (International Symposium on Computer Architecture)
- Cooperative Caching for Chip Multiprocessors (International Symposium on Computer Architecture)
- Space/time trade-offs in hash coding with allowable errors
- SimpleScalar: An Infrastructure for Computer System Modeling (Computer)
- POWER5 system microarchitecture (IBM Journal of Research and Development)
- Data prefetch mechanisms (CSUR)
Their papers
- Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (2006) — 380 citations