High-performance CMOS variability in the 65-nm regime and beyond

By K. Bernstein, D. Frank, A. Gattiker, Wilfried E. Haensch, B. Ji, S. Nassif, Edward J. Nowak, D. Pearson, N. Rohrer. IBM Journal of Research and Development, 2006

707 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/c7d764fc8bd7fd81a72c643cada5c561130d01d1

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In Electrical and Electronic Engineering

1. Gareth Roy
2. Asen Asenov
3. Andrew R. Brown
4. Xingsheng Wang
5. Farinaz Koushanfar
6. Arturo Geigel

Citations in the corpus

• Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study (2011, background): “However, further scaling faces an increasing number of technological and physical challenges, among which statistical variability has become one of the major sources of concern for the industry [6], [ 7 ].”
• Active Hardware Metering for Intellectual Property Protection and Security (2007, background): “provide a classification of device variations (beyond 65nm) [4].”
• Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia (2008, methodology): “Therefore, the requirements that allow to reach the bit-fail probability P =( 1/10 000) × (1/Nbit) can be calculated [ 13 ], [14] (see Table VII).”
• Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture (2007, methodology): “As illustrated in Table II, the addition of the poly-Si granularity to the aforementioned two sources brings the simulated value for σVT closer to the measured values in similar devices [ 2 ], [31]–[33].”