Heavy ion-induced digital single-event transients in deep submicron Processes

By J. Benedetto, P. Eaton, K. Avery, D. Mavis, M. Gadlage, T. Turflinger, P. Dodd, G. Vizkelethyd. IEEE Transactions on Nuclear Science, 2004

139 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/113fe95e245bef22dbaf3e344bd10b4ac03ef60b

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In Electrical and Electronic Engineering

Citations in the corpus

Single Event Transients in Digital CMOS—A Review (2013, background): “Example of DSET test structure from [36], [38].”
On-Chip Characterization of Single-Event Transient Pulsewidths (2006, background): “25 μm and smaller technologies, SETs in combinational logic will dominate single-event related reliability issues [6].”
Production and propagation of single-event transients in high-speed digital logic ICs (2004, methodology): “For ICs with unhardened embedded memories, the observed error rate may therefore be frequencyindependent, while for ICs with hardened latches or little embedded memory the frequency-dependent error rate characteristic of captured DSETs emerges [11].”
Radiation-induced soft errors in advanced semiconductor technologies (2005, background): “Radiation events occurring in combinational logic result in the generation of single event transients (SET) that, if propagated and latched into a memory element, will lead to a soft error [6].”
Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology (2008, methodology): “25- m, SET errors have become dominant in circuits that use SEU-hardened static-latch cells [67]–[69].”
Digital Single Event Transient Trends With Technology Node Scaling (2006, background): “work [2] that shows that DICE chains capture additional SETs as the operating frequency is increased.”
RHBD techniques for mitigating effects of single-event hits using guard-gates (2005, background): “25 m and smaller technologies, SETs in combinational logic will dominate single-event related reliability issues [6].”
Current and Future Challenges in Radiation Effects on CMOS Electronics (2010, background): “More recent data confirms the existence of DSETs in numerous technologies, including high-speed GaAs FET [51], Si bipolar [52], and Si CMOS logic circuitry [53], [54].”