Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology

By R. Lacoe. IEEE Transactions on Nuclear Science, 2008

151 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

Evolution of Total Ionizing Dose Effects in MOS Devices With Moore’s Law Scaling (2018, background): “With progressive technology scaling, thicknesses of isolation oxides also have decreased [6], [7], [12], leading to a general”
Radiation-Induced Short Channel (RISCE) and Narrow Channel (RINCE) Effects in 65 and 130 nm MOSFETs (2015, background): “However, HBD techniques were required to prevent the opening of large leakage current paths [5].”
Single Event Transients in Digital CMOS—A Review (2013, background): “Specific hardening-by-design rules, such as frequent well contacts, dummy junctions, etc [60], can be used to reduce the parasitic bipolar amplification and the resulting transient current.”
Current and Future Challenges in Radiation Effects on CMOS Electronics (2010, background): “example a gate region that is annular, completely surrounding the drain with the source in turn surrounding the gate [39].”