RHBD techniques for mitigating effects of single-event hits using guard-gates

By A. Balasubramanian, B. Bhuva, J. D. Black, Lloyd W. Massengill. IEEE Transactions on Nuclear Science, 2005

145 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/67add2d86bfc3ebbd851b8e1290aab6427018742

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. R. Lacoe
2. Pascale Gouker
3. Véronique Ferlet-Cavrois
4. Lloyd W. Massengill
5. J. Benedetto
6. D. Fleetwood
7. Paul E. Dodd

In Hardware and Architecture

1. R. Lacoe
2. Pascale Gouker
3. Véronique Ferlet-Cavrois
4. Lloyd W. Massengill
5. Paul E. Dodd

Citations in the corpus

• Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology (2008, methodology): “It has recently been proposed to apply guard gates to improve the SEU performance of DICE cell designs [71].”
• Single Event Transients in Digital CMOS—A Review (2013, methodology): “[137] of this technique, as shown in Fig.”
• Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies (2007, background): “Circuit level hardening techniques, such as temporal redundancy [8], guard gates, or glitch filtering [9], require SET pulse-widths to be below a particular circuit timing threshold in order to be effective—the choice of timing threshold often significantly impacts overall circuit performance.”