Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

By Bin Yang, K. Buddharaju, S. Teo, Navab Singh, Guo-Qiang Lo, D. Kwong. IEEE Electron Device Letters, 2008

222 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/793b627006fc27da615840e162ff1f16d0be233a

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Biomedical Engineering

1. Kaustav Banerjee

In Electrical and Electronic Engineering

1. Sungjoo Lee
2. Zhixian Chen
3. Kaustav Banerjee
4. Kota Murali
5. R. Pandey
6. Hong Li
7. Navin Srivastava
8. Chuan Xu

Citations in the corpus

• Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature (2011, background): “(∼70 mV/V) is achieved as a result of excellent gate control by GAA structure [4], [11], and [12].”
• A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance (2011, background): “It is well understood that at such a tunnel distance BTBT current has to be extremely low, which is responsible for the device’s excellent OFF-state behavior.”
• Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires (2009, methodology): “was fabricated by either chemical synthesis [18] or using fully CMOS-compatible technology [19], have been demonstrated.”