Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

By Z.X. Chen, H. Yu, N. Singh, N. Shen, R. Sayanthan, Guo-Qiang Lo, D. Kwong. IEEE Electron Device Letters, 2009

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Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing (2013, background): “in the linear region ID−VD characteristics [11], [15] caused by the large tunnel resistance across the tunneling junction.”
CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing (2011, background): “Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.”
Doping-Less Tunnel Field Effect Transistor: Design and Investigation (2013, background): “This problem is being extensively studied using strain, hetero-structures, low bandgap materials, high-k gate insulators, and nanowires [6], [11]–[14].”
Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature (2011, background): “(∼70 mV/V) is achieved as a result of excellent gate control by GAA structure [4], [11], and [12].”
Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability (2016, methodology): “To calibrate the models the GAA TFET has been designed with the same device parameters as shown in ref [21].”