Band-to-band tunneling in carbon nanotube field-effect transistors.

By Joerg Appenzeller, Yu-ming Lin, Joachim Knoch, Phaedon Avouris. Physical Review Letters, 2004

809 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Materials Chemistry

View Paper: https://www.semanticscholar.org/paper/3639fc5f4b2f028af5faa95aed5cf17dea9866bb

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Citations in the corpus

Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions (2010, background): “In addition, tunnel fieldeffect transistors (TFETs) should show a very small leakage current, in the range of femtoamperes [2], due to the large tunneling barrier formed when the device is turned off.”
Tunnel field-effect transistors as energy-efficient electronic switches (2011, background): “Recently, TFETs fabricated in various material systems (carbon, silicon, SiGe and group III–V materials”
Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design (2005, methodology): “controlled tunneling for switching and that in this way it is possible to achieve S-values smaller than 60mV/dec at roomtemperature [25].”
Low-subthreshold-swing tunnel transistors (2006, methodology): “[5], a subthreshold swing of 40 mV/dec was measured in a doublegated transistor in which interband tunnel current flows through”
Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping (2016, background): “tubes [10], germanium (Ge) source TFETs [11], and indium arsenide (InAs)-based TFETs [12].”
Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric (2007, background): “One such reported device is the Tunnel FET that incorporates a delta-layer of SiGe at the edge of the p+ region, in order to reduce the barrier width and, thereby, improve the subthreshold swing and ON-current [10], [11].”
Tunnel Field-Effect Transistors in 2-D Transition Metal Dichalcogenide Materials (2015, background): “…Bozidar Novakovic1, Gerhard Klimeck1, Rajib Rahman1, and Joerg Appenzeller2 1Network for Computational Nanotechnology, Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA 2Birck Nanotechnology Center, Department of Electrical and Computer…”
Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits (2009, background): “It can be observed that all of the CMOS-based transistors [Bulk, FinFET, and fully-depleted silicon-on-insulator (FDSOI)] have S values ≥ 60 mV/dec (= 2.3 kT/q) at room temperature, while the nanowire field-effect transistor (NWFET) [4], the carbonnanotube-based tunnel field-effect transistor (T-CNF”
Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions (2008, background): “HERE has been a recent interest in the exploration of tunneling field-effect transistors (TFETs), where gatecontrolled band-to-band tunneling (BBT) is expected to reduce the subthreshold swing (SS) below the thermal limit of ln(10)kT /q per decade, enabling transistor operation at voltages below 0.5”