Si tunnel transistors with a novel silicided source and 46mV/dec swing
By K. Jeon, W. Loh, P. Patel, C. Kang, Jungwoo Oh, A. Bowonder, Chanro Park, Casey Smith, P. Majhi, H. Tseng and 3 more. Symposium on VLSI Technology, 2010
196 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/a45b5c46c9b93443b8d3a759a7bef393071c827d
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In Electrical and Electronic Engineering
- Alan C. Seabaugh
- Kaustav Banerjee
- Luca Selmi
- Sungjoo Lee
- Zhixian Chen
- Navab Singh
- G. Ramanathan
- David Esseni
Citations in the corpus
- Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets (2012, background): “His research interests include the fabrication and characterization of CMOS compatible TFETs.”
- CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing (2011, background): “Although there are a few TFETs reporting lower than 50 mV/decade using carbon nanotubes [3], heterostructures [4], or complex TFET structures [ 5 ], achieving SS < 50 mV/decade has been challenging in most of the fabricated TFETs [7], [9], [10].”
- Tunnel Field-Effect Transistors: State-of-the-Art (2014, background): “are given for Si in [26], [29], [31] and for InGaAs in [47].”
- Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors (2013, background): “5 V) for the n-TFET are obtained, distinctly higher than for most reported Si TFETs [7], [9], [10], [15], [16].”