Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance
By F. Mayer, C. L. Royer, J. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, S. Deleonibus. 2008 IEEE International Electron Devices Meeting, 2008
292 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/734aa13a24e132969dcbc51948fc0244f103c4ec
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Citations in the corpus
- Tunnel Field-Effect Transistors: State-of-the-Art (2014, result): “Consistent with theoretical predictions, experimental Si TFETs [25]–[30] generally display lower ON-currents.”
- Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors (2013, background): “III–V [3], SiGe [4], [5], and Ge [4], [6] provide higher tunneling probabilities because of their small Eg .”
- A Comparative Study on the Impacts of Interface Traps on Tunneling FET and MOSFET (2014, unknown): “, III-V semiconductors) [6]–[8], employing the inserted”
- Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets (2012, background): “His research interests include the fabrication and characterization of CMOS compatible TFETs.”
- Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature (2011, result): “It should be noted that ambipolar conduction, which is an issue in TFET devices [3], [9], is not observed in our results.”
- CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing (2011, background): “Although there are a few TFETs reporting lower than 50 mV/decade using carbon nanotubes [3], heterostructures [ 4 ], or complex TFET structures [5], achieving SS < 50 mV/decade has been challenging in most of the fabricated TFETs [7], [9], [10].”