Partha Bhattacharyya
IEEE Transactions on Very Large Scale Integration (vlsi) Systems · with Dandapat · 2015
A researcher in the Science corpus: 1 paper; trusts 0 researchers and is trusted by 0 researchers here, as inferred from the citation graph.
Whom Partha Bhattacharyya trusts overall
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Papers from Partha Bhattacharyya's perspective
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- Performance analysis of low-power 1-bit CMOS full adder cells (IEEE Transactions on Very Large Scale Integration (vlsi) Systems)
- Low-voltage low-power CMOS full adder
- Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates
- A review of 0.18-μm full adder performances for tree structured arithmetic circuits (IEEE Transactions on Very Large Scale Integration (vlsi) Systems)
- Digital Integrated Circuits A Design Perspective
- CMOS VLSI Design: A Circuits and Systems Perspective
- CMOS Full-Adders for Energy-Efficient Arithmetic Applications (IEEE Transactions on Very Large Scale Integration (vlsi) Systems)
- Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style (IEEE Transactions on Very Large Scale Integration (vlsi) Systems)
- The emotional characteristics of teaching: an ethnographic study of one teacher
- A Study Of Mathematics Anxiety in Pre-Service Teachers
Their papers
- Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit (2015) — 318 citations