A review of 0.18-μm full adder performances for tree structured arithmetic circuits

By Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2005

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Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style (2006, methodology): “The proposed circuit uses only 2% more area when compared to the circuit in [7] but the circuit in [9] uses 43% more area.”
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit (2015, methodology): “Standard static complementary metal–oxide–semiconductor (CMOS) [3], dynamic CMOS logic [4], complementary pass-transistor logic (CPL) [5], [6], and transmission gate full adder (TGA) [7], [8] are the most important logic design styles in the conventional domain.”
CMOS Full-Adders for Energy-Efficient Arithmetic Applications (2011, result): “We compared the performance of 7 full-adders, named: new14T [15], hpsc [7], hybrid [8], hybrid cmos [9], cpl [10], Ours1 and Ours2.”