Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

By Sumeer Goel, Ashok Kumar, Magdy A. Bayoumi. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2006

518 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/26bd6feff9e3ed70fe584c16f4cf65afdddc54f8

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In Biomedical Engineering

1. Mariano Aguirre-Hernandez
2. Mónico Linares Aranda

In Electrical and Electronic Engineering

1. Mariano Aguirre-Hernandez
2. Mónico Linares Aranda

Citations in the corpus

• CMOS Full-Adders for Energy-Efficient Arithmetic Applications (2011, methodology): “…the logic style (standard CMOS [2], differential cascode voltage switch (DCVS) [3], complementary pass-transistor logic (CPL) [4], double pass-transistor logic (DPL) [5], swing restored CPL (SR-CPL) [6], and hybrid styles [7]–[9]), and the logic structure used to build the adder module [10], [11].”