Low-voltage low-power CMOS full adder

By D. Radhakrishnan. 2001

404 citations recorded by the source corpus.

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CMOS Full-Adders for Energy-Efficient Arithmetic Applications (2011, result): “We compared the performance of 7 full-adders, named: new14T [15], hpsc [7], hybrid [8], hybrid cmos [9], cpl [10], Ours1 and Ours2.”
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits (2004, methodology): “There are several designs [1], [11]–[15] of the modules, as shown in Fig.”
A review of 0.18-μm full adder performances for tree structured arithmetic circuits (2005, methodology): “It has been a common practice to treat the adder cell as a stand alone cell in simulation [10], [14], [16], [17].”
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style (2006, methodology): “This circuit has been widely used to build full-adder cells [7], [8].”
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit (2015, methodology): “Standard static complementary metal–oxide–semiconductor (CMOS) [3], dynamic CMOS logic [4], complementary pass-transistor logic (CPL) [5], [6], and transmission gate full adder (TGA) [7], [8] are the most important logic design styles in the conventional domain.”
A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits (2005, methodology): “It has been a common practice to treat the adder cell as a stand alone cell in simulation [10], [14], [16], [17].”