Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates

By H. Bui, Yuke Wang, Yingtao Jiang. 2002

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Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style (2006, methodology): “These circuits are used to build 41 ten-transistor adders and are presented in [1].”
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit (2015, methodology): “When compared with the best design in terms of area (10 T) [24], the proposed design of the adder (excluding buffer) consumed 44.5% more area.”
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits (2004, methodology): “There are several designs [1], [11]–[15] of the modules, as shown in Fig.”
A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits (2005, methodology): “It has been a common practice to treat the adder cell as a stand alone cell in simulation [10], [14], [16], [17].”
A review of 0.18-μm full adder performances for tree structured arithmetic circuits (2005, methodology): “It has been a common practice to treat the adder cell as a stand alone cell in simulation [10], [14], [16], [17].”