Performance analysis of low-power 1-bit CMOS full adder cells

By A. Shams, T. Darwish, Magdy A. Bayoumi. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2002

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A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits (2005, methodology): “Therefore, the adder cells must possess sufficient drivability to provide the next cell with clean inputs [ 5 ].”
A review of 0.18-μm full adder performances for tree structured arithmetic circuits (2005, methodology): “Several variants of static CMOS logic styles have been used to implement low-power 1-b adder cells [5], [10]–[12].”
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style (2006, methodology): “These circuits have been used in many adders for both module I [6], [14] and module II [14].”
CMOS Full-Adders for Energy-Efficient Arithmetic Applications (2011, methodology): “This simulation environment has been used for comparing the full-adders analyzed in [9], [14], with the addition of the inverters at the outputs.”
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit (2015, background): “The prime disadvantage of CPL, that is, the voltage degradation was successfully addressed in TGA, which uses only 20 transistors for full adder implementation [7], [8].”
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits (2004, methodology): “5(b) is able to operate at low voltage, but it is not power efficient [13]–[15].”