CMOS Full-Adders for Energy-Efficient Arithmetic Applications

By Mariano Aguirre-Hernandez, Mónico Linares Aranda. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2011

376 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/b043e8d2a93ab608c1c2cf6d66d2944f21d461e5

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In Electrical and Electronic Engineering

1. Anup Dandapat
2. Partha Bhattacharyya
3. Bijoy Kundu
4. Vinay Kumar
5. Sovan Ghosh

Citations in the corpus

• Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit (2015, methodology): “The proposed hybrid full adder has also been compared with other hybrid full adders reported in [1], [2], and [19].”