Digital Integrated Circuits A Design Perspective

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The physics of optical computing (2023, background): “46,47) and small digital-electronic circuits can be clocked at rates >5 GHz, but both analog and digital electronics for computing systems tend to be limited to speeds ≪ 5 GHz by wire delays 48,49 and, since the mid-2000s, also by power dissipation 23 .”
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit (2015, background): “Another complementary type smart design is the mirror adder [4] with almost same power consumption and transistor count (as that of [3]) but the maximum carry propagation path/delay inside the adder is relatively smaller than that of the standard CMOS full adder.”
Dynamic Computation Offloading for Mobile-Edge Computing With Energy Harvesting Devices (2016, methodology): “The frequencies scheduled for the W CPU cycles in the t th time slot are denoted as f tw , w = 1 , · · · , W , which can be implemented by adjusting the chip voltage with DVFS techniques [29].”
Fundamental Green Tradeoffs: Progresses, Challenges, and Impacts on 5G Networks (2016, background): “To cope with the heterogeneous applications in 5G networks, a homogeneous implementation principle only relying on software defined properties may fail to achieve the best EE performance because the dynamic circuit power of the homogeneous hardware system is proportional to the square of clock frequ”