Piranha: a scalable architecture based on single-chip multiprocessing

By Luiz André Barroso, K. Gharachorloo, Robert McNamara, A. Nowatzyk, Shaz Qadeer, B. Sano, Scott Smith, R. Stets, Ben Verghese. Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000

600 citations recorded by the source corpus.

This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multiprocessing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/0af8c168f4423535773afea201c05a9e63ee9515

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Citations in the corpus

Robust non-linear control through neuroevolution (2003, methodology): “Commercial CMPs have already started to emerge including the IBM Power4 processor (Diefendorff 1999), which has two processing cores per die, the eight-core Compaq Piranha (Barroso et al. 2000), and many other designs are currently being studied in academia, e.”
AVIO: detecting atomicity violations via access interleaving invariants (2006, unknown): “Piranha: a scalable architecture based on single-chip multiprocessing.”
Cooperative Caching for Chip Multiprocessors (2006, background): “Proposed CMP designs [5, 19, 32] have emphasized minimizing the number of off-chip accesses and thus have used a banked, shared L2 cache organization.”
Managing Wire Delay in Large Chip-Multiprocessor Caches (2004, background): “Larger-scale CMPs seem like to follow as transistor densities increase [5, 18, 45, 28].”
A NUCA Substrate for Flexible CMP Cache Sharing (2007, methodology): “For instance, the dual-processor Power4 CMP [23] uses three banks, and the eight-processor Piranha CMP uses eight banks for each L2 cache.”
Heterogeneous chip multiprocessors (2005, background): “(1) The original core and ( 2 ) a conjoinedcore pair, both showing floating-point unit routing.”
Single-ISA heterogeneous multi-core architectures for multithreaded workload performance (2004, result): “Piranha: A scalable architecture based on single-chip multiprocessing.”
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors (2007, background): “Its Piranha-style cache hierarchy [1] consists of private L1s and a logically shared L2 organized as 16 independent banks.”
Optimizing replication, communication, and capacity allocation in CMPs (2005, methodology): “[ 4 ] showed that the L1 tag copies in Piranha incur a 4% overhead in total on-chip cache capacity.”