A static power model for architects

By J. A. Butts, G. Sohi. Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000, 2000

435 citations recorded by the source corpus.

Static power dissipation due to transistor leakage constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the contribution will increase rapidly, reaching one half of total power dissipation within three process generations. Developing power efficient products will require consideration of static power in the earliest phases of design, including architecture and microarchitecture definition. We propose a simple equation for estimating static power consumption at the architectural level: P/sub static/=V/sub CC//spl middot/N/spl middot/k/sub design//spl middot/I/spl circ//sub leak/, where V/sub CC/ is the supply voltage, N is the number of transistors, k/sub design/ is a design dependent parameter, and I/spl circ//sub leak/ is a technology dependent parameter. This model enables high-level reasoning about the likely static power demands of alternative microarchitectures. Reasonably accurate values for the factors within the equation may be obtained directly from the high-level designs or by straightforward scaling arguments. The factors within the equation also suggest opportunities for static power optimization, including reducing the total number of devices, partitioning the design to allow for lower supply voltages or slower, less leaky transistors, turning off unused devices, favoring certain design styles, and favoring high bandwidth over low latency. Speculation is also examined as a means to employ slower transistors without a significant performance penalty.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/f461923eed6a1da9bf0c690e70f92de928d3cc40

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Citations in the corpus

Cooperative Caching for Chip Multiprocessors (2006, background): “For example, power can be saved by ”turning off” selected portions of the aggregate on-chip cache, or using higher threshold voltage [20] (leading to slower accesses), while reliability can be improved via spatial redundancy (e.”
HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects (2003, background): “In this section, we briefly review the Butts and Sohi model and then describe how HotLeakage is derived.”
Orion: a power-performance simulator for interconnection networks (2002, background): “Power models and simulators for processors and memories have been proposed [3, 4, 25], enabling a rich body of research into power-efficient mechanisms [2, 18].”
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors (2007, methodology): “We use the static power model proposed by Butts and Sohi [3], which uses a nominal leakage value along with estimates of the number of transistors (scaled by some design-dependent factors) in each microarchitectural structure.”
Power reduction techniques for microprocessor systems (2005, background): “Despite these advantages, V. Venkatachalam and M. Franz Figure adapted from Butts and Sohi 2000. there are issues to consider such as the costs of the hardware used to cool the circuit.”
An integrated GPU power and performance model (2010, background): “Butts and Sohi [6] presented the following simplified leakage power model for an architecture-level study.”