Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

By Kathryn W. Guarini, Anna W. Topol, M. Ieong, R. Yu, L. Shi, M. Newport, D. Frank, D.V. Singh, G. Cohen, S. Nitta and 6 more. Digest. International Electron Devices Meeting,, 2002

139 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/137903540c199958e35d633c44510ab6d26707c7

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In Electrical and Electronic Engineering

1. Jian-Qiang Lu
2. Arvind Kumar
3. Gabriel H. Loh
4. Kathryn W. Guarini

Citations in the corpus

• Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections (2006, background): “Three-dimensional (3-D) LSI satisfies these requirements, and thus, it has been attracting considerable attention from many researchers in the LSI device and package technology areas [1]–[9].”
• 3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems (2009, background): “Vol. 97, No. 1, January 2009 | Proceedings of the IEEE 21 materials, such as nonoutgassing adhesives [21], [25], [32], [43], [45], [47]–[49], plasma-enhanced chemical vapor deposition (PECVD) oxide [ 24 ], [26], and few metals (e.g., copper [23], [27]–[31], titanium [50], [51], InAu [33], and CuSn [”
• 3D-Stacked Memory Architectures for Multi-core Processors (2008, background): “There are many candidate technologies for 3D die stacking, but wafer-to-wafer bonding appears to be the leading contender in industry [6, 15, 32].”
• Three-dimensional integrated circuits (2006, methodology): “Among other measurements [16], we examined median data for a particular wafer at three stages: a) after standard CMOS fabrication; b) after an additional ‘‘simulated’’ lamination process in which the pressure and temperature required to adhere the processed wafer to glass are applied without actuall”
• 3D silicon integration (2008, methodology): “Examples of TSV research published from IBM include: (i) small sizes and silicon thickness of 11 , 12], (ii) 1 to 20 um diameter or width and silicon thickness of a few microns to about 100 um thickness [13, 14], and (iii) large TSV with 20 um to 90 um diameter and silicon thickness of 50 to 300 um”