Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs

By R. Patti. Proceedings of the IEEE, 2006

576 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/3db2cb0d82f27112f10d0f7bf58182e1ddddf8f6

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Biomedical Engineering

1. Erik Jan Marinissen
2. Yervant Zorian
3. Jian-Qiang Lu

In Electrical and Electronic Engineering

1. Erik Jan Marinissen
2. Yervant Zorian
3. Jian-Qiang Lu

Citations in the corpus

• Testing 3D chips containing through-silicon vias (2009, background): “The latest evolution in this list of innovations is the so-called three-dimensional stacked IC (3D-SIC); a single package containing a vertical stack of naked dies which are interconnected by means of Through-Silicon Vias (TSVs) [1–3].”
• 3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems (2009, methodology): “Many research groups are exploring its potential applications, such as improving interconnect delay [55]–[60], [93], memory stacks [ 29 ], [59], [61], memory-processor or logic–logic stacks [29], [62]–[65], signal-processing circuits [66], [67], field-programmable gate arrays (FPGAs) [68], [69], ima”