Embedded deterministic test

By J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004

528 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/4296885a8090e80ae5063c0e6cbe775e9dd39e66

How researchers see this paper

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In Electrical and Electronic Engineering

1. Erik Jan Marinissen
2. Yervant Zorian

Citations in the corpus

• Testing 3D chips containing through-silicon vias (2009, background): “It allows to reduce the volume of both test stimuli and responses (and the corresponding test length) with one or two orders of magnitude [44].”