3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

By B. Swinnen, W. Ruythooren, P. D. Moor, L. Bogaerts, L. Carbonell, K. D. Munck, B. Eyckens, S. Stoukatch, D. Tezcan, Z. Tőkei and 3 more. International Electron Devices Meeting, 2006

203 citations recorded by the source corpus.

Subfields: Atomic and Molecular Physics, and Optics, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/da0e0894c5b121284243375ca092992b6b398573

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Erik Jan Marinissen
2. Yervant Zorian
3. Jian-Qiang Lu

Citations in the corpus

• 3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems (2009, methodology): “Other approaches are also demonstrated with TSVs as a thinning stopper, where the TSVs are formed either during the FEOL process [29] or after the BEOL process but right before wafer alignment and bonding [36], [ 53 ].”
• 3D stacked IC demonstration using a through Silicon Via First approach (2008, methodology): “Our 3D Stacked IC (3D-SIC) process [4-5] uses IC foundry infrastructure to create Through Silicon Vias (TSVs) prior to BEOL processing.”
• Testing 3D chips containing through-silicon vias (2009, background): “These TSVs are cylindrical copper nails of 25μm height, 5μm diameter (i.e., an aspect ratio of 5:1), and have a minimum pitch of 10μm [ 15 , 16].”