Testing 3D chips containing through-silicon vias

By Erik Jan Marinissen, Yervant Zorian. International Test Conference, 2009

323 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/6da4adda74cc2bd7c72b84f2714e19ee3378e8e3