I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q

By K. Gopalakrishnan, Peter B. Griffin, James D. Plummer. Digest. International Electron Devices Meeting,, 2002

370 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/2d1bd08ce1783d4b660d770b34d4b87da39c8199

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In Electrical and Electronic Engineering

Citations in the corpus

Toward Nanowire Electronics (2008, background): “…to smaller NW diameters and gate oxide thickness in a wrap-gate architecture, we find that for feasible oxide thickness and NW diameter of dox ≤ 2 nm and dnw ≤ 10 nm in a wrapgate architecture, tunnel Si NW-FETs exhibiting an S smaller than 60 mV/dec in a limited Vgs-range can be obtained.”
Impact ionization MOS (I-MOS)-Part II: experimental results (2005, methodology): “In order to verify that the I-MOS has a subthreshold slope that is steeper than “kT/q,” Si-based n-channel and p-channel devices were fabricated in the Stanford Nanofabrication Facility (SNF) [ 1 ].”
Impact ionization MOS (I-MOS)-Part I: device and circuit simulations (2005, methodology): “Previously [29], we have shown using simulations than a properly sized I-MOS inverter can have a FO delay at 400 K of approximately 10 ps with a static power that is at least”
Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits (2009, background): “It can be observed that all of the CMOS-based transistors [Bulk, FinFET, and fully-depleted silicon-on-insulator (FDSOI)] have S values ≥ 60 mV/dec (= 2.3 kT/q) at room temperature, while the nanowire field-effect transistor (NWFET) [4], the carbonnanotube-based tunnel field-effect transistor (T-CNF”
A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance (2011, background): “impact-ionization MOSFETs (I-MOSFET) [3], and TFETs [4] have been demonstrated to minimize SCE and to lower the source–drain leakage current.”
Low-Voltage Tunnel Transistors for Beyond CMOS Logic (2010, neutral): “Switching mechanisms that can achieve less than 60 mV/decade in a FET structure include tunneling [4]–[6], impact ionization [ 7 ]–[10], ferroelectric dielectrics [11], or mechanical gates [12]–[14].”