Yatin Vasant Hoskote
Computer Networks and Communications · 2007–2010
A researcher in the Science corpus: 5 papers; trusts 4 researchers and is trusted by 0 researchers here, as inferred from the citation graph.
Subfields
- Computer Networks and Communications — 35 citations into it
- Hardware and Architecture — 27 citations into it
Whom Yatin Vasant Hoskote trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Papers from Yatin Vasant Hoskote's perspective
Ordered by how strongly the researchers Yatin Vasant Hoskote trusts endorse each paper. Same corpus, a different order for every researcher.
- Route packets, not wires: on-chip interconnection networks (Proceedings - Design Automation Conference)
- Orion: a power-performance simulator for interconnection networks (35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.)
- Energy-aware mapping for tile-based NoC architectures under performance constraints (Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.)
- Theory of latency-insensitive design (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.)
- Bandwidth-constrained mapping of cores onto NoC architectures (Proceedings Design, Automation and Test in Europe Conference and Exhibition)
- Dynamic voltage scaling with links for power optimization of interconnection networks (The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.)
- A survey of research and practices of Network-on-chip (CSUR)
- Energy- and performance-aware mapping for regular NoC architectures (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)
- Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip (Proceedings Design, Automation and Test in Europe Conference and Exhibition)
- ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (Micro)
Their papers
- A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS (2010) — 714 citations
- An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS (2007) — 743 citations
- Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009) — 750 citations
- An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS (2008) — 751 citations
- A 5-GHz Mesh Interconnect for a Teraflops Processor (2007) — 726 citations