A survey of research and practices of Network-on-chip

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Cross-layer optimization for energy-efficient wireless communications: a survey (2009, background): “This important trend is also studied in the context of interconnection structures, giving rise to high-performance, low power consumption networks on chip [33].”
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, background): “In [21], the authors provide a comprehensive introduction to NoCs and existing design practices.”
Nanonetworks: A new communication paradigm (2008, background): “In the recent literature, the term ‘‘nanonetworks” refers to electronic components and their interconnection within a single chip on a nano-scale [12].”
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters (2011, background): “Networks-on-Chip (NoC) [7], provide bandwidth scalability, but the latency of traditional NoCs is not adequate for L1 processor-to-memory communication [8], and highly optimized special-purpose interconnects are required.”
Flattened Butterfly Topology for On-Chip Networks (2007, background): “On-chip interconnection networks have recently attracted considerable research attention [5], much of which has focused on microarchitecture improvements [1,19] and routing algorithms [22].”