Dynamic voltage scaling with links for power optimization of interconnection networks

By L. Shang, Li-Shiuan Peh, Niraj Kumar Jha. The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings., 2003

492 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/badaed2af28c7b9b0c37aecf9095c9cab9669d00

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In Computer Networks and Communications

In Electrical and Electronic Engineering

In Hardware and Architecture

Citations in the corpus

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, background): “[145], as well as shutting links down based on their actual utilization [80], [155].”
Flattened butterfly: a cost-efficient topology for high-radix networks (2007, background): “There have been many research efforts to reduce the power consumption through different techniques [12, 25, 29].”
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (2006, background): “This ominous trend has been observed by several researchers [1, 5, 8] and the realization of its ramifications has fueled momentum in investigating NoC architectures.”
rCUDA: Reducing the number of GPU-based accelerators in high performance clusters (2010, background): “Several proposals from academia have been made in this field trying to lower the voltage and frequency of unused links [19, 20], or even turning them off [21].”