Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
By Mikael Millberg, Erland Nilsson, Rikard Thid, Axel Jantsch. Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004
421 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/2380e112413d4b5090cb09d13adcfe1f51664198
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Ümit Y. Ogras
- Radu Marculescu
- Onur Mutlu
- Thomas Moscibroda
- Li-Shiuan Peh
- Yatin Vasant Hoskote
- Natalie D. Enright Jerger
- Goran Konjevod
In Electrical and Electronic Engineering
- Onur Mutlu
- Ümit Y. Ogras
- Radu Marculescu
- Thomas Moscibroda
- Goran Konjevod
- Karam S. Chatha
- K. Srinivasan
- Li-Shiuan Peh
In Hardware and Architecture
- Ümit Y. Ogras
- Onur Mutlu
- Radu Marculescu
- Thomas Moscibroda
- Li-Shiuan Peh
- Natalie D. Enright Jerger
- Yatin Vasant Hoskote
- Jingcao Hu
Citations in the corpus
- Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, background): “While it is relatively easy to find the communication latency for guaranteed service traffic [42], [108], analyzing the average latency for best effort traffic is a challenging task.”
- A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip (2005, neutral): “Other NoCs which implement GS are ÆTHEREAL [8] and NOSTRUM [11].”
- Key research problems in NoC design: a holistic perspective (2005, background): “Moreover, guaranteed service operation, as required by some applications, is relatively easier to satisfy by using circuit switching [33,34] as opposed to wormhole routing [31,32].”
- Linear programming based techniques for synthesis of network-on-chip architectures (2006, background): “[26] [27] , AEthereal [28] [29] and Vellanki et al.”
- A case for bufferless routing in on-chip networks (2009, background): “Deflection routing in on-chip networks: Several recent studies [38, 31, 19, 18] examined the use of bufferless deflection routing in on-chip networks.”