An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

By S. Vangal, J. Howard, G. Ruhl, Saurabh Dighe, H. Wilson, J. Tschanz, D. Finan, Priya Iyer, Arvind P. Singh, Tiju Jacob and 4 more. 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007

743 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/27732e2d5bc50654050bfcdd32f8ad3d9ba5d115

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Citations in the corpus

Flattened Butterfly Topology for On-Chip Networks (2007, methodology): “For example, in the 2-D mesh network used in the Intel TeraFlop [25], with uniform random traffic, Th is approximately 3 times Ts and for worst case traffic, there is approximately 10× difference.”
The multikernel: a new OS architecture for scalable multicore systems (2009, background): “Furthermore, many multicore processors have already demonstrated the use of non-coherent shared memory [15, 26, 68], and Mattson et al.”
Thousand Core ChipsA Technology Perspective (2007, background): “Figure 9: Three dimensional interconnect with stack ing A three dimensional integration (3D) of a memory wi th processor is a potential solution, where a thinned m mory die is placed between the processor and the package [4].”
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS (2010, methodology): “The design is organized in a 6×4 2D-array of tiles [3] to increase scalability.”
Corona: System Implications of Emerging Nanophotonic Technology (2008, neutral): “The 80-core Intel Polaris chip [31] and the 64-core MIT Raw processor [29] connect their cores with 2D mesh networks.”
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, methodology): “Intel is already prototyping an 80-core processor [30, 38] and there is speculation that entire dies in a 3D package may be employed for large SRAM caches or DRAM main memory [7, 23, 30].”
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation (2009, neutral): “on fundamental NoC concepts was demonstrated [15].”
An operating system for multicore and clouds: mechanisms and implementation (2010, background): “In this regard, fault tolerance in modern OSes designed for multicore is becoming an essential requirement.”
Efficient implementation of sorting on multi-core SIMD CPU architecture (2008, background): “For example, there are commercial products that have 8 cores on the same chip [10], and there is a research prototype with 80 cores [24].”
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS (2008, background): “2) contains 80 tiles arranged as an 8 10 2-D mesh network that is designed to operate at 4 GHz [7].”
A 5-GHz Mesh Interconnect for a Teraflops Processor (2007, neutral): “Teraflops Processor The Teraflops Processor architecture contains 80 tiles arranged in a 2D array and connected by a mesh network that is designed to operate at 5 GHz (see Figure 1).(8) A tile consists of a processing engine connected to a five-port router, which forwards packets between tiles.”
Factored operating systems (fos): the case for a scalable operating system for multicores (2009, background): “Categories and Subject Descriptors D.4.7[Operating Systems]: Organization and Design General Terms Operating System Design, Multicore Computers Keywords Multicore Operating Systems, Factored Operating System 1.”
Mapping on multi/many-core systems: Survey of current and emerging trends (2013, methodology): “Different large scale architectures have already been introduced, like Invasive Computing [32], Angstrom [34], and Intel’s TeraFlop [91].”