An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
By S. Vangal, J. Howard, G. Ruhl, Saurabh Dighe, H. Wilson, J. Tschanz, D. Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain and 5 more. IEEE Journal of Solid-State Circuits, 2008
751 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/4e0087e68a612fb2c7df3e01cfa9e05a63bf5d9d
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In Computer Networks and Communications
Citations in the corpus
- State-of-the-art in heterogeneous computing (2010, methodology): “[163] demonstrated one teraflops performance whilst using a mere 97 watts of power on the Intel Teraflops Research Chip [164].”
- The 48-core SCC Processor: the Programmer's View (2010, methodology): “The first processor in this program was the 80-core TeraScale processor [2].”
- Graphics processing unit (GPU) programming strategies and trends in GPU computing (2013, background): “Intel have also developed other highly parallel architectures, including the Larrabee [21] based on simple and power-efficient x86 cores, the Single-chip Cloud Computer (SCC) [10], and the 80-core tera-scale research chip Polaris [24].”
- Firefly: illuminating future network-on-chip with nanophotonics (2009, methodology): “With the prevalence of dual-core and quad-core processors in the market, researchers could not help projecting a many-core era with tens, hundreds, or even thousands of cores integrated on a single chip [14, 6, 37].”