A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

By J. Howard, Saurabh Dighe, Yatin Vasant Hoskote, S. Vangal, D. Finan, G. Ruhl, D. Jenkins, H. Wilson, Nitin Borkar, G. Schrom and 20 more. IEEE International Solid-State Circuits Conference, 2010

714 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/15e07d192d360652e68e38b4ba267e160f972390

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Citations in the corpus

The 48-core SCC Processor: the Programmer's View (2010, methodology): “The SCC hardware was described elsewhere [4].”
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks (2016, methodology): “Conventional approaches usually use hop-by-hop mesh NoC at the cost of increased ramp-up time and router overhead [34], [35].”
Architecture support for disciplined approximate programming (2012, methodology): “Fine-grained voltage adjustments can be performed after fabrication using off-chip voltage regulators as in the Intel SCC [13] or by on-chip voltage regulators as proposed by Kim et al.”