Orion: a power-performance simulator for interconnection networks

By Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik. 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings., 2002

844 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electronic, Optical and Magnetic Materials, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/b1658fb0778e9cc86e461fdc55c272c3483bba7e

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Citations in the corpus

SUNMAP: a tool for automatic topology selection and generation for NoCs (2004, methodology): “We used ORION [22], a power modeling tool, for developing bit energy models for the switches.”
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip (2005, methodology): “We used ORION [37], a power modeling tool, for developing bit energy models for the switches.”
A case for bufferless routing in on-chip networks (2009, methodology): “We use the Orion energy model [23], assuming 100nm technology and 2GHz @ 1.”
Express virtual channels: towards the ideal interconnection fabric (2007, background): “Orion [19], an architecture-level network energy model, to evaluate the energy consumption of routers and links.”
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors (2008, methodology): “Table 3 reports the values of the energy spent in these operations (buffer reading and writing energies are combined, arbiter energy is neglected) that were obtained with the ORION NoC simulator [45].”
"It's a small world after all": NoC performance optimization via long-range link insertion (2006, methodology): “Furthermore, the Orion model [40] integrated to our simulator shows about 5% savings in the overall energy consumption.”
PowerPack: Energy Profiling and Analysis of High-Performance Systems and Applications (2010, background): “Most existing power profiling research is focused on a single computer component such as processor [6], [36], disk [37], memory [36], and networking interface [35].”
Linear programming based techniques for synthesis of network-on-chip architectures (2006, background): “The existing work on NoC design has chiefly concentrated on performance evaluation [4] [6] [7], router architecture design [8] [9], designer specified network instantiation [10], and error control [11] [12].”
GARNET: A detailed on-chip network model inside a full-system simulator (2009, methodology): “Network power: GARNET has the Orion power models [30] incorporated.”
Full-System Power Analysis and Modeling for Server Environments (2006, background): “Current approaches to power modeling fall into two broad classes: measurements of power at the hardware level [8], [1 3], [11] or modeling of power at the simulation level [5], [7], [9 ], [14], [22], [26], [27], [29].”
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006, methodology): “Previous work on NoCs focused on task mapping [14], energy management [36], and reliability [21].”
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors (2006, methodology): “We use Orion [ 54 ] to estimate the area of input and output buers, as well as the crossbar areas inside the switches.”
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling (2012, methodology): “To address shortcomings of these existing tools, we propose DSENT to provide a unified electrical and optical framework that can be used to model system-scale aggressive electrical and opto-electronic NoCs in future technology nodes.”