The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs

By Michael B. Taylor, J. Kim, Jason E. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, Henry Hoffmann, Paul R. Johnson, Jae W. Lee, Walter Lee and 8 more. IEEE Micro, 2002

384 citations recorded by the source corpus.

Wire delay is emerging as the natural limiter to microprocessor scalability. A new architectural approach could solve this problem, as well as deliver unprecedented performance, energy efficiency and cost effectiveness. The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip. An architecture that has direct, first-class analogs to all of these physical resources will ultimately let programmers achieve the maximum amount of performance and energy efficiency in the face of wire delay.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/d589123c9665f52c1c06a0b3c80aa94c423a8908

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Citations in the corpus

Reconfigurable computing: architectures and design methods (2005, methodology): “Finally we identify and summarise the main trends.”
Linear programming based techniques for synthesis of network-on-chip architectures (2006, methodology): “They are suitable for general purpose architectures, such as the RAW processor [ 6 ] that include homogeneous cores.”
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS (2008, methodology): “multiprocessors include the RAW [3], TRIPS [4], and ASAP [5] projects.”
Dynamic voltage scaling with links for power optimization of interconnection networks (2003, background): “In recent years, interconnection network fabrics, historically used in high-end multiprocessor systems [17], have proliferated to a wide range of communication systems – clusters [1], terabit Internet routers [5], server blades [9, 16], and on-chip networks [6, 24].”
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs (2006, background): “We target the Raw microprocessor [37, 40], which addresses the wire delay problem by providing direct instruction set architecture (ISA) analogs to three underlying physical resources of the processor: gates, wires and pins.”