M.Jagadesh Kumar1

IEEE transactions on nanotechnology · 2005

A researcher in the Science corpus: 1 paper; trusts 1 researcher and is trusted by 0 researchers here, as inferred from the citation graph.

Whom M.Jagadesh Kumar1 trusts

Their strongest outbound trust, strongest first, inferred from their citations.

  1. Mamidala Jagadesh Kumar (in Electrical and Electronic Engineering)

Papers from M.Jagadesh Kumar1's perspective

Ordered by how strongly the researchers M.Jagadesh Kumar1 trusts endorse each paper. Same corpus, a different order for every researcher.

  1. Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review (IEEE transactions on device and materials reliability)
  2. Device scaling limits of Si MOSFETs and their application dependencies (Proceedings of the IEEE)
  3. Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors (2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104))
  4. Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs (IEEE Electron Device Letters)
  5. On the performance limits for Si MOSFETs: a theoretical study
  6. Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs (IEEE International Electron Devices Meeting 2003)
  7. Long-range Coulomb interactions in small Si devices. Part I: Performance and reliability
  8. Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm (Digest. International Electron Devices Meeting,)
  9. The effective drive current in CMOS inverters (Digest. International Electron Devices Meeting,)
  10. Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness

Their papers