Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs

By S. Oh, D. Monroe, J. Hergenrother. IEEE Electron Device Letters, 2000

346 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/7ab7b51b9e13ef78c8f32efd6e5f7876ce2bf69b

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In Electrical and Electronic Engineering

Citations in the corpus

Device scaling limits of Si MOSFETs and their application dependencies (2001, background): “gate wraps around it cylindrically has the best electrostatic scaling properties of all and has been investigated by several groups [30], [31], but may prove to be impractical because of the high quantization energy levels for such a channel.”
Low-Voltage Tunnel Transistors for Beyond CMOS Logic (2010, neutral): “13 compares the computed electrostatic length [88] by solution of the Laplace equation for several FET geometries [89].”
Analytic Model for the Surface Potential and Drain Current in Negative Capacitance Field-Effect Transistors (2010, background): “For a DG-MOSFET, this condition holds for L> 2λ, where L is the channel length, and λ is the characteristic length over which the source and the drain perturb the channel potential, and could be estimated as λ ∼ (ts + 2(es/eox)EOT)/π, where the term between the parentheses represents the effective d”
Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application (2001, background): “out that an adequate scaling of the buried oxide thickness of SOI transistors is also important in order to control SCE [ 11 ] and to reduce the threshold voltage fluctuations due to possible variations [12], [13].”
A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs (2002, methodology): “ [ 7 ] T. Kolding, “On-wafer calibration techniques for giga-hertz CMOS mea-”
Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs (2010, background): “MOSFETs predict that the short-channel effects improve when the relevant body dimensions are shrunk [2]–[6].”
The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance (2005, background): “As illustrated in Table 1(b) and described in the following, a variety of multiple-gate nonclassical CMOS structures [53]–[92] have been proposed and demonstrated to help manage electrostatic integrity (i.”
Modeling and Simulation Investigation of Sensitivity of Symmetric Split Gate Junctionless FET for Biosensing Application (2017, methodology): “In order to reduce this impact, numerous multigate devices have been proposed such as Double Gate (DG) MOSFET, Surrounding-Gate/Gate All Around (SG/GAA) MOSFET and Fin-FETs, which can suppress the SCEs and improve gate controllability [16], [17].”
A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements (2015, background): “Good agreement is observed for tox > d/2, while the approximation given in [42] works better for tox < d/2.”
Scaling of Nanowire Transistors (2008, background): “The scale length for nanowire MOSFETs can also be derived [25] with Bessel functions for the case of cylindrical coordinates [26].”