On-Chip Interconnection Architecture of the Tile Processor

By D. Wentzlaff, P. Griffin, H. Hoffmann, Liewei Bao, B. Edwards, C. Ramey, M. Mattina, Chyi-Chang Miao, John F. Brown, A. Agarwal. IEEE Micro, 2007

349 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

Technology-Driven, Highly-Scalable Dragonfly Topology (2008, background): “From large scale systems [1, 19, 27] to multicore architectures [17, 33], the interconnection network that connects processors and memory modules significantly impacts the overall performance and cost of the system.”
A case for bufferless routing in on-chip networks (2009, background): “chip multi-processors or their prototypes [24], [19], [14] .”
A detailed and flexible cycle-accurate Network-on-Chip simulator (2013, background): “This approach has been shown to be attractive for many NoC use cases both in research and in the industry [28], [29].”
The multikernel: a new OS architecture for scalable multicore systems (2009, background): “As a result, it is a distinct possibility that future operating systems will have to handle non-coherent memory [12, 49, 69], or will be able to realize substantial performance gains by bypassing the cache-coherence protocol [70].”
Graphite: A distributed parallel simulator for multicores (2010, methodology): “The default simulator configuration also uses separate models for application and memory traffic, as is commonly done in multicore chips [13], [15].”
An operating system for multicore and clouds: mechanisms and implementation (2010, background): “In this regard, fault tolerance in modern OSes designed for multicore is becoming an essential requirement.”