Modeling the effect of technology trends on the soft error rate of combinational logic

By Premkishore Shivakumar, M. Kistler, S. Keckler, Doug Burger, Lorenzo Alvisi. Proceedings : International Conference on Dependable Systems and Networks, 2002

1,584 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/ebcc39cadec9b37d709c8820d96710ac722c4dab

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Citations in the corpus

Zyzzyva (2007, background): “non-fail-stop behavior in real systems [2, 5, 6, 27, 30, 32, 36, 39, 40] suggest that BFT may yield significant benefits even without resorting to n-version programming [4, 15, 33].”
Silent Data Corruptions at Scale (2021, background): “With increased silicon density and technology scaling [31], [13], we believe that academic researchers and industry should invest in methods to counter these issues.”
Gate sizing to radiation harden combinational logic (2006, background): “In the next decade, technology trends—smaller feature sizes, lower voltage levels, higher operating frequencies, and reduced logic depth—are projected to cause an increase in the soft error failure rate in core combinational logic in integrated circuits [5], [18], [22], [33].”
Characterization of soft errors caused by single event upsets in CMOS processes (2004, background): “It has been argued that, with an increasing clock frequency and a higher level of pipelining, the contribution of the logic will dominate the chip-level SER [ 96 ].”
Soft Error Susceptibilities of 22 nm Tri-Gate Devices (2012, background): “projected more than 10 years ago [15] (Fig.”
Radiation-induced soft errors in advanced semiconductor technologies (2005, result): “Similar findings (based on simulation) were reported by others [32].”
Characterizing the effects of transient faults on a high-performance processor pipeline (2004, background): “Isolating latches from all of pipeline state has significance on several fronts: First, latches may have different fault rates and fault models from RAM structures due to implementation differences [17].”
Shoestring: probabilistic soft error reliability on the cheap (2010, methodology): “[29] has reported that the SER for SRAM cells is expected to remain stable, while the SER for logic is steadily rising.”
Cost-effective approach for reducing soft error failure rate in logic circuits (2003, methodology): “In a recent study, it has been projected that by 201 1, the soft error rate in logic circuits will be comparable to that of unprotected memory elements [Shivakumar 021.”
The soft error problem: an architectural perspective (2005, neutral): “At present the contribution of static logic to the overall error rate is assumed to be small, but Shivakumar, et al. [ 14 ] predict that contribution of static logic will soon equal that of latches.”
SWIFT: software implemented fault tolerance (2005, background): “While these devices yield performance enhancements, they will be less reliable [23], making processors that use them more susceptible to transient faults.”
Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices (2006, background): “40 90 140 Technology node (nm) N or m al iz ed S ER [15] [14] [3] this work [20]”
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, background): “, [153]) can potentially be relevant to router microarchitectures as well.”
The effects of energy management on reliability in real-time embedded systems (2004, methodology): “…per second on each chip (assuming a 100 megabit chip) and (cid:14) 2 (cid:158)6ˇ to (cid:14) 2 (cid:158) / faults per second in a system [21], [23], [29]. y z(cid:28)(cid:12)—(cid:14) 2 (cid:158)6ˇ -6(cid:5)(cid:8)(cid:7)(cid:11)(cid:9) In this work, we assume that at voltage and frequency…”