The soft error problem: an architectural perspective

By Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt. International Symposium on High-Performance Computer Architecture, 2005

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Zyzzyva (2007, background): “non-fail-stop behavior in real systems [2, 5, 6, 27, 30, 32, 36, 39, 40] suggest that BFT may yield significant benefits even without resorting to n-version programming [4, 15, 33].”
DRAM errors in the wild: a large-scale field study (2009, background): “Errors in dynamic random access memory (DRAM) devices have been a concern for a long time [3,11,15–17 , 23 ].”
Overview and status of metal S/D Schottky-barrier MOSFET technology (2006, background): “This is a significant technology advantage for highly scaled CMOS, which is becoming increasingly sensitive to parasitic bipolar action and soft errors for both memory and logic devices [54], [55].”
OCEAN (2014, background): “Hence a portion of the errors are masked and do not require any correcting action Krishnamohan and Mahapatra 2005; Lee et al. 2008; Mukherjee et al. 2005].”
Silent Data Corruptions at Scale (2021, background): “In a collaboration study between Intel and University of Michigan [28] radiation induced soft errors are identified to not reflect a permanent failure.”