Characterizing the effects of transient faults on a high-performance processor pipeline

By Nicholas J. Wang, Justin Quek, Todd M. Rafacz, Sanjay J. Patel. International Conference on Dependable Systems and Networks, 2004, 2004

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Techniques to reduce the soft error rate of a high-performance microprocessor (2004, methodology): “[31] describe alternate ways to compute AVFs using statistical fault injection into RTL models.”
ReStore: symptom based soft error detection in microprocessors (2005, methodology): “In our previous work [28], we observed that a very large fraction of simulated transient errors injected into the latches and RAM cells of a modern processor pipeline (using a Verilog processor model) were logically masked before they could adversely”
Shoestring: probabilistic soft error reliability on the cheap (2010, background): “[38] showed that the bulk of transient-induced failures are dominated by corruptions introduced from injections into the register file.”
The case for lifetime reliability-aware microprocessors (2004, methodology): “Scaling decreases lifetime reliability by shrinking the thickness of gate and inter layer dielectrics, increasing current density in interconnects, and by raising processor temperature which exponentially accelerates wear-out failures.”