Cost-effective approach for reducing soft error failure rate in logic circuits

By Kartik Mohanram, N. Touba. International Test Conference, 2003. Proceedings. ITC 2003., 2003

304 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/2bab356b120ee2423f0fe8d3e9d0d1e38bab339a

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Pascale Gouker
2. Véronique Ferlet-Cavrois
3. Lloyd W. Massengill
4. Quming Zhou
5. Kartik Mohanram

In Hardware and Architecture

1. Pascale Gouker
2. Véronique Ferlet-Cavrois
3. Lloyd W. Massengill
4. Quming Zhou
5. Kartik Mohanram

Citations in the corpus

• Single Event Transients in Digital CMOS—A Review (2013, methodology): “[132] proposed techniques to target gate redundancy to the combinational logic”
• Gate sizing to radiation harden combinational logic (2006, background): “In [25], it was shown that as a result of these factors, the soft error susceptibility of internal nodes (which is the contribution of the node to the overall soft error failure rate) in a logic circuit can vary by an order of magnitude or more.”