Sanjay J. Patel

Hardware and Architecture · 2004–2010

A researcher in the Science corpus: 3 papers; trusts 5 researchers and is trusted by 2 researchers here, as inferred from the citation graph.

Subfields

• Hardware and Architecture — 14 citations into it; #1,324 of 1,551 by trust here, #954 by citations
• Electrical and Electronic Engineering — 10 citations into it; #13,732 of 16,539 by trust here, #12,727 by citations
• Computer Networks and Communications — 9 citations into it

Whom Sanjay J. Patel trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. Shubhendu S. Mukherjee
2. Nicholas J. Wang
3. Steven K. Reinhardt

Who trusts Sanjay J. Patel overall

1. Nicholas J. Wang
2. Shubu Mukherjee

Papers from Sanjay J. Patel's perspective

Ordered by how strongly the researchers Sanjay J. Patel trusts endorse each paper. Same corpus, a different order for every researcher.

1. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor (Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.)
2. Modeling the effect of technology trends on the soft error rate of combinational logic (Proceedings : International Conference on Dependable Systems and Networks)
3. The microarchitecture of the Pentium 4 processor
4. Impact of CMOS technology scaling on the atmospheric neutron soft error rate
5. Detailed design and evaluation of redundant multi-threading alternatives (Proceedings 29th Annual International Symposium on Computer Architecture)
6. Characterizing the effects of transient faults on a high-performance processor pipeline (International Conference on Dependable Systems and Networks, 2004)
7. Techniques to reduce the soft error rate of a high-performance microprocessor (Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.)
8. Characterization of soft errors caused by single event upsets in CMOS processes (IEEE Transactions on Dependable and Secure Computing)
9. Robust system design with built-in soft-error resilience (Computer)
10. Checkpoint processing and recovery: towards scalable large instruction window processors (Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.)

Their papers

• Characterizing the effects of transient faults on a high-performance processor pipeline (2004) — 423 citations
• ReStore: symptom based soft error detection in microprocessors (2005) — 320 citations
• An adaptive performance modeling tool for GPU architectures (2010) — 335 citations